1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device, and more particularly relate to a semiconductor device including a DLL (Delay Locked Loop) circuit that generates a phase-controlled internal clock signal.
2. Description of Related Art
A phase-controlled internal clock signal is needed sometimes in a semiconductor device that operates in synchronization with a clock signal, such as a synchronous DRAM (Dynamic Random Access Memory). The phase-controlled internal clock signal is often generated by a DLL circuit (see Japanese Patent Application Laid-open No. 2010-124020).
A state in which a phase-control led internal clock signal that is correctly controlled is output from the DLL circuit is referred to as “lock state”. A maximum period from when the DLL circuit is reset to when the DLL circuit reaches the lock state (a maximum lock cycle) is defined by the specifications.
However, the maximum lock cycle is defined based on the number of cycles of a clock signal. Therefore, in a case of using a high-frequency clock signal, it is sometimes difficult to bring the DLL circuit into the lock state within the maximum lock cycle.